1. Field of the Invention
The present invention relates to a voltage drop circuit for decreasing a supply voltage, and applies the dropped voltage to a ROM.
2. Description of Related Art
FIG. 8 is a circuit diagram showing a conventional voltage drop circuit. In FIG. 8, the reference numeral 1 designates a control circuit for activating one of an active voltage supply circuit 2 or a standby voltage supply circuit 6 in response to the operation mode of a CPU to a ROM 11; 2 designates the active voltage supply circuit for generating a dropped voltage (drain voltage Vd) by decreasing a supply voltage, and for regulating fluctuations of the active voltage applied to the ROM 11; 3 designates an external power supply; 4 designates a comparator for comparing the drain voltage Vd of a transistor 5 with a reference voltage V.sub.REF in response to a start command sent from the control circuit 1, and for controlling the on-state resistance of the transistor 5; and 5 designates the P-channel transistor (simply referred to as the transistor from now on) whose on-state resistance is increased when the drain voltage Vd is higher than the reference voltage V.sub.REF, and is decreased when the drain voltage Vd is lower than the reference voltage V.sub.REF.
The reference numeral 6 designates the standby voltage supply circuit for generating a dropped voltage by decreasing a supply voltage from an external power supply 7; 8 designates a pull-up resistor; 9 designates a switch that turns on in response to a start command from the control circuit 1; 10 designates a ROM power supply using the dropped voltage produced by the active voltage supply circuit 2 or standby voltage supply circuit 6; and 11 designates the ROM.
Next, the operation of the conventional voltage drop circuit will be described.
For example, when a CPU not shown in this figure enters an access mode of the ROM 11, the control circuit 1 supplies the active voltage supply circuit 2 with a start command so that the CPU can access the ROM 11 by placing it in an active mode. This places the output level of the control circuit 1 at the supply voltage level, the active voltage supply circuit 2 in the active mode, and the standby voltage supply circuit 6 in an inactive mode (because the switch 9 in the standby voltage supply circuit 6 is turned off).
The comparator 4 in the active voltage supply circuit 2 compares, in response to the start command from the control circuit 1, the drain voltage Vd of the transistor 5 with the predetermined reference voltage V.sub.REF, and causes, when the drain voltage Vd is lower than the reference voltage V.sub.REF, the transistor 5 to reduce its on-state resistance in order to increase the active voltage applied to the ROM 11, which is reduced by an increase of the current consumption of the ROM 11. Thus, the drain voltage Vd of the transistor 5 increases, and the active voltage applied to the ROM 11 rises to a predetermined voltage (3 V, for example).
On the other hand, the comparator 4 causes, when the drain voltage Vd is higher than the reference voltage V.sub.REF, the transistor 5 to increase its on-state resistance in order to decrease the active voltage applied to the ROM 11, which is increased by a decrease of the current consumption of the ROM 11. Thus, the drain voltage Vd of the transistor 5 decreases, and the active voltage applied to the ROM 11 falls to the predetermined voltage.
When the CPU enters a mode in which it does not access the ROM 11, or executes a stop instruction, the control circuit 1, which consists of an inverter 12 as shown in FIG. 9, for example, places the ROM 11 in a standby mode, and produces a start command to activate the standby voltage supply circuit 6 to reduce the current consumption of the ROM 11. This places the output level of the control circuit 1 at the ground level, the standby voltage supply circuit 6 in the active mode, and the active voltage supply circuit 2 in the inactive mode because the comparator 4 in the active voltage supply circuit 2 turns off the transistor 5.
Thus, the switch 9 in the standby voltage supply circuit 6 turns on in response to the start command from the control circuit 1, and the pull-up resistor 8 decreases the supply voltage from the external power supply 7, and applies the dropped voltage to the ROM power supply 10. As a result, the ROM power supply 10 applies a fixed standby voltage (3 V, for example) to the ROM 11 with a fixed standby current.
With the foregoing configuration, the conventional voltage drop circuit can regulate fluctuations of the active voltage applied to the ROM 11 due to the fluctuations in the current consumption of the ROM 11. To achieve quick response in regulating the fluctuations, however, an increasing current must be supplied to the comparator 4, and this presents a problem of increasing the current consumption of the active voltage supply circuit 2.
Furthermore, although the ROM 11 becomes accessible from the CPU when the ROM 11 shifts from the standby mode to the active mode, it is not improbable that the CPU cannot read data correctly from the ROM 11 for a moment immediately after the control circuit 1 issues the start command because the dropped voltage is not yet settled at that time.